Differential comparison circuit

ABSTRACT

A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage.  
     Input/output terminals I/O 1  and I/O 2  of a latch circuit  1  are connected to the drain terminals of MOS transistors M 1  and M 2  having the same characteristics. Input terminals IN 1  and IN 2  are provided to the gate and source terminals of the MOS transistor M 2,  and input terminals IN 3  and IN 4  are provided to the gate and source terminals of the MOS transistor M 2.  A bias circuit  2  brings the MOS transistors M 1  and M 2  into the same bias state. The difference of the input signals supplied to the input terminals IN 1  and IN 2  is compared with the difference of the input signals supplied to the input terminals IN 3  and IN 4.  Since the comparison result is outputted from the first and second input/output terminals I/O 1  and I/O 2,  the input offset voltage does not affect the differential comparison circuit. Therefore, the differential comparison circuit can set the reference voltage to the differential signal and can easily obtain required accuracy.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a differential comparison circuit forcomparing differential signals.

[0003] 2. Description of the Related Art

[0004] A comparison circuit for comparing differential signals has beenused at present for a pipeline system A/D converter, for example. Thispipeline system A/D converter is constituted by cascading a plurality ofsample-and-hold circuits and acquires each bit value of the leastsignificant bit (LSB) from the most significant bit (MSB) of pulse codemodulation (PCM) data from comparison circuits arranged at theirjunctions. More concretely, the pipeline system A/D converter has theconstruction shown in FIG. 4. A sample-and-hold circuit SH is composedof a completely differential type operational amplifier 41, and aplurality of these circuits SH is cascaded. In other words, outputterminals out1 and out2 of a sample-and-hold circuit SH of a precedingstage are connected to input terminals in1 and in2 of a sample-and-holdcircuit SH of a subsequent stage. The completely differential typeoperational amplifier 41 generates the differential signals from theoutput terminals out1 and out 2. These signals are output signals Vout1and Vout2 that are the analog signals inverted mutually with a voltageequilibrium point V1 of both output terminals as the center as shown inFIG. 5. The voltage equilibrium point V1 is accomplished by arrangingfeedback circuits having the same phase, not shown in the drawing, atthe output terminals out1 and out2 and by adjusting the output bias ofthe completely differential type operational amplifier 41.

[0005] Each comparison circuit 42 is disposed at the junction betweenthe sample-and-hold circuit SH of a preceding stage and thesample-and-hold circuit SH of a subsequent stage. A comparator 52 of thecomparison circuit 42 compares the output voltage of the sample-and-holdcircuit SH of the preceding stage with a predetermined reference voltageequal to the voltage equilibrium point V1, or the voltages at outputterminals out1 and out2 of the sample-and-hold circuit of the precedingstage with each other, to thereby judge “1” and “0” and outputs theresult from the output terminal C0. When this judgment value is “1”, thesample-and-hold circuit SH of the subsequent stage outputs the voltagevalue that is twice the difference obtained by subtracting the voltagevalue corresponding to the judgment value “1” from the output voltage ofthe sample-and-hold circuit SH of the preceding stage. When the judgmentvalue is “0”, the sample-and-hold circuit SH of the subsequent stageoutputs the voltage value that is twice the difference obtained bysubtracting the voltage value corresponding to the judgment value “0”from the output voltage of the sample-and-hold circuit SH of thepreceding stage. Such a sample-and-hold operation is conducted asswitching of a plurality of capacitances, not shown, connected to switchcapacitance networks CS1 and CS2 and reset switches RS1 and RS2interposed between the output terminals out1 and out2 and the inputterminals in1 and in2 of the sample-and-hold circuit SH is effected.When such comparison operation and sample-and-hold operation areconducted, the analog signals are applied to the sample-and-hold circuitSH of the initial stage, and the comparison circuits 42 from the initialto last stages output each bit value of LSB from MSB of the PCM data,respectively. Each comparison circuit 42 includes an input amplitudemonitor unit for monitoring whether or not the input signal of thesample-and-hold circuit SH is within a suitable allowable input range,in addition to a comparator 52 for conducting the comparison operationdescribed above. The sample-and-hold circuit SH transmits therein theanalog signals to the input terminals in1 and in2 through the switchcapacitance networks CS1 and CS2 to the differential input terminals ofthe completely differential type operational amplifier 41. Therefore,the suitable input range is determined by the differential amplituderather than by the absolute value. The prior art technology expressesthe predetermined amplitude value by use of the absolute value of thereference voltage as will be explained below.

[0006] In the comparison circuit 42, the input amplitude monitor unitcomprises comparators 43, 44, 47 and 48, inverters 45 and 49, AND gates46 and 50 and an OR gate 51. The comparator 43 compares the outputsignal Vout1 with the reference voltage Vref1 (=1.5 V). The comparator44 compares the output signal Vout2 with the reference voltage Vref2(=0.5 V). The comparator 47 compares the output signal Vout1 with thereference voltage Vref2. The comparator 48 compares the output signalVout2 with the reference voltage Vref1. The output from the comparator43 is given to one of the terminals of the AND gate 46. The output fromthe comparator 44 is given to the other terminal of the AND gate 46through the inverter 45. When the output signals Vout1 and Vout2 areabove 1.5 V and below 0.5 V, respectively, the comparator 43 outputs thelogic level “1”, the comparator 44 outputs the logic level “0” and theAND gate 46 outputs the logic level “1”. Similarly, when the outputsignals Vout1 and Vout2 are below 0.5 V and above 1.5 V, respectively,the AND gate 50 outputs the logic level “1”. Therefore, the OR gate 51in this embodiment output the logic level “1” notifying the excess ofthe allowable input range from the output terminal OVER when theamplitude difference between the output signals Vout1 and vout2 isgreater than 1 V.

[0007] However, the comparison circuit 42 shown in FIG. 4 cannot makethe most of the advantage of the differential signals created by theoutput signals Vout1 and Vout2. For example, fluctuation of the powersource voltage and of the voltage equilibrium point V1 does not greatlyaffect the difference of the amplitude values of the output signalsVout1 and Vout2, but the output signals vout1 and Vout2 per se aregreatly affected by such fluctuation. Since the comparison circuit42compares these output signals Vout1 and Vout2 as the discrete voltageswith the predetermined reference voltages Vref1 and Vref2, thecomparison result is likely to be affected by the fluctuation of thepower source voltage and the voltage equilibrium point V1. When thevoltage equilibrium point V1 shown in FIG. 5 shifts up or down, forexample, the erroneous operation develops in any of the comparators 43,44, 47 and 48.

SUMMARY OF THE INVENTION

[0008] It is therefore an object of the present invention to provide adifferential comparison circuit capable of easily acquiring desiredcircuit accuracy and capable of comparing differential signals withsmaller influences of fluctuation of a power source voltage and avoltage equilibrium point.

[0009] A differential comparison circuit according to the presentinvention comprises a first MOS transistor using its gate terminal as afirst input terminal and its source terminal as a second input terminal;a second MOS transistor having the same conduction type as that of thefirst MOS transistor, and using its gate terminal as a third inputterminal and its source terminal as a fourth input terminal; a latchcircuit having its first input/output terminal connected to a drainterminal of the first MOS transistor and its second input/outputterminal connected to a drain terminal of the second MOS transistor; anda bias circuit for bringing the first and second MOS transistor into thesame bias condition; wherein the difference of the input signalssupplied to the first and second input terminals is compared with thedifference of the input signals supplied to the third and fourth inputterminals, and a comparison result is outputted from the first andsecond input/output terminals.

[0010] Preferably, the bias circuit described above includes a firstcurrent source connected between the source terminal of the first MOStransistor and a first power source terminal, a second current sourceconnected between the drain terminal of the first MOS transistor and asecond power source terminal, a third current source connected betweenthe source terminal of the second MOS transistor and the first powersource terminal, and a fourth current source connected between the drainterminal of the second MOS transistor and the second power sourceterminal, and the first and second power source terminals have mutuallyopposite polarities.

[0011] Preferably, the bias circuit described above includes a commoncurrent source connected between the drain terminal and the power sourceterminal of each of the first and second MOS transistors. Preferably,the bias circuit described above includes active loads of third andfourth MOS transistors interposed between the drain terminals of thefirst and second MOS transistors and the current sources, respectively,the third and fourth MOS transistors have an opposite conduction type tothat of the first and second MOS transistors, the drain of each of thethird and fourth MOS transistors is connected to the drain of each ofthe first and second MOS transistors, and the source of each of thethird and fourth MOS transistors is connected to each of the currentsources.

[0012] Preferably, the differential comparison circuit further comprisesa first source follower interposed between the first input terminal andthe gate terminal of the first MOS transistor, and having its inputterminal connected to the first input terminal and its output terminalconnected to the gate terminal of the first MOS transistor; a secondsource follower interposed between the second input terminal and thesource terminal of the first MOS transistor, and having its inputterminal connected to the second input terminal and its output terminalconnected to the source terminal of the first MOS transistor; a thirdsource follower interposed between the third input terminal and the gateterminal of the second MOS transistor, and having its input terminalconnected to the third input terminal and its output terminal connectedto the gate terminal of the second MOS transistor; and a fourth sourcefollower interposed between the fourth input terminal and the sourceterminal of the second MOS transistor, and having its input terminalconnected to the fourth input terminal and its output terminal connectedto the source terminal of second MOS transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a circuit diagram showing a construction of adifferential comparison circuit according to a first embodiment of thepresent invention;

[0014]FIG. 2 is a circuit diagram showing a construction of adifferential comparison circuit according to a second embodiment of thepresent invention;

[0015]FIG. 3 is a circuit diagram showing a construction of adifferential comparison circuit according to a third embodiment of thepresent invention;

[0016]FIG. 4 is a circuit diagram showing a construction of adifferential comparison circuit according to the prior art; and

[0017]FIG. 5 is a waveform diagram useful for explaining an example of adifferential signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, several preferred embodiments of the presentinvention will be explained in detail with reference to the accompanyingdrawings. FIG. 1 is a circuit diagram showing a construction of adifferential comparison circuit according to a first embodiment.

[0019] First and second MOS transistors Ml and M2 are N channel MOStransistors that are fabricated into the same size to obtain the samecharacteristics. The first MOS transistor M1 has first and second inputterminals IN1 and IN2 at its gate and source terminals, respectively.These input terminals IN1 and In2 receive input signals Vg₁ and Vs₁ thatare differential signals relative to each other. The second MOStransistor M2 has third and fourth input terminals IN3 and IN4 at itsgate and source terminals, respectively. These input terminals IN1 andIN2 receive input signals Vg₂ and Vs₂ that are differential signals toeach other. The drain terminals of the first and second MOS transistorsM1 and M2 are connected to first and second input/output terminals I/O1and I/O2, respectively, and also to a bias circuit 2. The substrates ofthe first and second MOS transistors M1 and M2 are connected to theirsource terminals. The source terminals of the first and second MOStransistors M1 and M2 are connected to the bias circuit 2. The biascondition of the first and second MOS transistors M1 and M2 is the same.

[0020] A latch circuit 1 includes a pair of inverters IV1 and IV2 havinginput and output terminals connected to one another to provide the firstand second input/output terminals I/O1 and I/O2, and a reset switch RSinterposed between the input/output terminals I/O1 and I/O2. Acomparison result of a differential component as the difference betweenthe input signals Vg₁ and Vs₁ with a differential component as thedifference between the input signals Vg₂ and Vs₂ is outputted as logiclevels from the first and second input/output terminals I/O1 and I/O2.When the reset switch RS is turned ON, the latched logic level is reset.

[0021] The bias circuit 2 includes first and second current sources I1and I2 each having one of the terminals thereof connected to the sourceand drain terminals of the first MOS transistor M1, and third and fourthcurrent sources I3 and I4 each having one of the ends thereof connectedto the source and drain terminals of the second MOS transistor M2. Theother terminal of each of the first and third current sources I1 and I3is connected to a power source terminal VSS (0 V) and the other terminalof each of the second and fourth current sources I2 and I4 is connectedto a power source terminal VDD (2 V).

[0022] Next, the operation of this embodiment will be explained.

[0023] The substrates of the first and second MOS transistors M1 and M2and the source terminal remain always at the same potential, and thesubstrate bias effect does not exist. Therefore, the source-drainvoltage of each of the first and second MOS transistors M1 and M2decides the condition of each MOS transistor M1, M2. Assuming herebythat input signals having the same amplitude (Vg-Vs) but havingdifferent offset potentials are applied to the gate-source of the firstand second MOS transistors, respectively, the conditions of the firstand second MOS transistors M1 and M2 are equal to each otherirrespective of the offset potentials. In other words, the same phasecomponent of the input signal Vg₁ and Vs₁ applied to the gate and thesource of the first MOS transistor M1 is removed, and only thedifferential component is taken out as the signal. This also holds trueof the second MOS transistor M2.

[0024] When the input values to the first and second MOS transistors Mland M2 are different in relation to the differential components of theinput signals Vg₁ and Vs₂, and the differential components of the inputsignals Vg₂ and Vs₂, the conditions of the first and second MOStransistors M1 and M2 are different, and the latch circuit 1 amplifiesthe difference of these differential components to the logic level andoutputs the difference so amplified.

[0025] In the manner described above, this embodiment can compare andoutput the difference between the differential component for the firstMOS transistor M1 and the differential component for the second MOStransistor M2. When, for example, the differential components of theinput signals Vg₂ and Vs₂ are the reference voltages, only thedifferential component needs be fixed. Therefore, in comparison with theprior art technology in which the reference voltages Vref1 and Vref2have the fixed values, this embodiment can obtain more easily thereference voltages having desired accuracy. In addition, even when theoffset potentials of the input signals Vg₁ and Vs₁ fluctuate due tofluctuation of the power source voltage, etc, no influence is exerted onthe differential components that are to be compared, and thedifferential signals can be compared with smaller influences of thefluctuation of the power source voltage, or the like.

[0026] Next, the second embodiment of the present invention will beexplained. FIG. 2 is a circuit diagram showing a construction of thisembodiment, wherein like reference numerals are used to identify likeconstituent elements as those used in FIG. 1. This also holds true ofthe later-appearing drawings. In this embodiment, first to fourth sourcefollower circuits SF1 to SF4 are interposed between the first to fourthinput terminals IN1 to IN4 and the first and second MOS transistors M1and M2, respectively, in order to prevent each differential inputterminal of each of the first and second MOS transistors Ml, M2, thatis, a signal path of each gate-source terminal, from serving as a DCload to the signal source, and to shift the input signal to a suitablesignal input level. The input terminal of each of the first to fourthsource follower circuits SF1 to SF4 is connected to each of the first tofourth input terminals IN1 to IN4 and its output terminal is connectedto each of the first and second MOS transistors M1 and M2.

[0027] A third MOS transistor M3 is interposed as an active load betweenthe first MOS transistor M1 and the second current source I2. Similarly,a fourth MOS transistor M4 is interposed as the active load between thesecond MOS transistor M2 and the fourth current source I4. The third andfourth MOS transistors M3 and M4 are P channel MOS transistors that havea conduction type opposite to that of the first and second MOStransistors Ml and M2.

[0028] This embodiment having such a construction exhibits the samefunction and effect as in the first embodiment. In addition, At sinceeach differential input terminal, that is, the signal path to each gateterminal or each source terminal, does not operate as the DC load to thesignal source, the operation speed can be improved and the input signalis allowed to shift to a suitable signal input level, thereby improvingthe input voltage range.

[0029] Next, the third embodiment of the present invention will beexplained. FIG. 3 is a circuit diagram showing a construction of thisembodiment. As shown in the circuit diagram, the first to fourth currentsources I1 to I4 are omitted but the third and fourth MOS transistors M3and M4 are connected to a common current source IC to constitute thecomparison output portion 3 into the differential construction. Thecomparison result of the differential components can be outputted as thedifferential signals from the first and second input/output terminalsI/O1 and I/O2. This embodiment having such a construction exhibits thesame function and effect as in the second embodiment, and can output thecomparison result of the differential components as the differentialsignals.

[0030] The present invention can compare the differential component asthe difference of two input signals with the differential component ofother two input signals. The present invention can easily acquire areference voltage having desired accuracy by using one of thedifferential components as the reference voltage and can highlyprecisely compare the differential components. In addition, even whenthe offset potential of each input signal fluctuates owing to thefluctuation of the power source voltage, or the like, no influence isexerted on each differential component to be compared. In other words,the present invention can compare the differential components withrestrained influences of the fluctuation of the power source voltage,etc, and can therefore provide a differential comparison circuit capableof easily acquiring desired circuit accuracy with smaller influences ofthe power source voltage.

What is claimed is:
 1. A differential comparison circuit comprising: afirst MOS transistor using a gate terminal thereof as a first inputterminal and a source terminal thereof as a second input terminal; asecond MOS transistor having the same conduction type as that of saidfirst MOS transistor, and using a gate terminal thereof as a third inputterminal and a source terminal thereof as a fourth input terminal; alatch circuit having a first input/output terminal thereof connected toa drain terminal of said first MOS transistor and a second input/outputterminal thereof connected to a drain terminal of said second MOStransistor; and a bias circuit for bringing said first and second MOStransistor into the same bias condition; wherein the difference of theinput signals supplied to said first and second input terminals iscompared with the difference of the input signals supplied to said thirdand fourth input terminals, and a comparison result is outputted fromsaid first and second input/output terminals.
 2. A differentialcomparison circuit according to claim 1, wherein said bias circuitincludes a first current source connected between the source terminal ofsaid first MOS transistor and a first power source terminal, a secondcurrent source connected between the drain terminal of said first MOStransistor and a second power source terminal, a third current sourceconnected between the source terminal of said second MOS transistor andsaid first power source terminal and a fourth current source connectedbetween the drain terminal of said second MOS transistor and said secondpower source terminal, and said first and second power source terminalshave mutually opposite polarities.
 3. A differential comparison circuitaccording to claim 1, wherein said bias circuit includes a commoncurrent source connected between the drain terminal and said powersource terminal of each of said first and second MOS transistors.
 4. Adifferential comparison circuit according to claim 2 or 3, wherein saidbias circuit includes active loads of third and fourth MOS transistorsinterposed between the drain terminals of said first and second MOStransistors and said current sources, respectively, said third andfourth MOS transistors have an opposite conduction type to that of saidfirst and second MOS transistors, the drain of each of said third andfourth MOS transistors is connected to the drain of each of said firstand second MOS transistors, and the source of each of said third andfourth MOS transistors is connected to each of said current sources. 5.A differential comparison circuit according to any of claims 1 through4, which further comprises: a first source follower interposed betweensaid first input terminal and the gate terminal of said first MOStransistor, and having an input terminal thereof connected to said firstinput terminal and an output terminal thereof connected to the gateterminal of said first MOS transistor; a second source followerinterposed between said second input terminal and the source terminal ofsaid first MOS transistor, and having an input terminal thereofconnected to said second input terminal and an output terminal thereofconnected to the source terminal of said first MOS transistor; a thirdsource follower interposed between said third input terminal and thegate terminal of said second MOS transistor, and having an inputterminal thereof connected to said third input terminal and an outputterminal thereof connected to the gate terminal of said second MOStransistor; and a fourth source follower interposed between said fourthinput terminal and the source terminal of said second MOS transistor,and having an input terminal thereof connected to said fourth inputterminal and an output terminal thereof connected to the source terminalof said second MOS transistor.